The present invention relates to the formation of dielectric layers. More particularly, embodiments of the present invention relate to a method for capping a low dielectric constant film that is particularly useful as a premetal or intermetal dielectric layer in an integrated circuit.
Semiconductor device geometries have dramatically decreased in size since integrated circuits were first introduced several decades ago, and all indications are that this trend will continue. Today's wafer fabrication plants are routinely producing devices having 0.25 μm and even 0.18 μm feature sizes, and the plants of the future will soon be producing devices having even smaller geometries.
The drive to faster and faster microprocessors, and more powerful microelectronic devices, is dependent on improvements in two chemistry-based areas, optical lithography and low dielectric constant materials. Several semiconductor manufacturers, materials suppliers and research organizations have focused on identifying low and extremely low dielectric constant films. As used herein, low dielectric constant materials are those films having a dielectric constant between 3.0 to 2.5 and extremely low dielectric constant (“ELK”) films are those films having a dielectric constant below 2.5 extending to dielectric constants below 2.0.
Several candidate low dielectric constant materials are currently under development. Certain specific organic, inorganic and hybrid dielectrics are amongst the current candidates. Additionally, dielectric films from these categories, when made porous, tend to have even lower dielectric constants, and are poised for integration in the next generation of interconnect structures. In terms of deposition techniques, both spin-on and chemical vapor deposition (“CVD”) processes are under development, with key challenges remaining around issues of technological performance—i.e. integration.
Among the organic material candidates, organic polymers such as polyarylene and polyarylethers have been most intensively pursued. Two examples of such materials include porous versions of Dow Chemical's SILK [a spin-on low k material (k between 2.6-2.8)] and FLARE from Allied Signal. Spin-on hydrogen silsesquioxane (“HSQ”) which has a dielectric constant of 2.9 (k=2.9), is an example of an inorganic dielectric material. Hybrid materials combine organic and inorganic materials. In hybrid materials, cross-linked silicon-oxygen containing polymers designated as polysiloxanes form the basis for conventional spin-on-glass (“SOG”) materials. One approach to achieving a lower dielectric constant in hybrid films has been to increase the amount of organic substitution in these materials. For example, where each silicon atom in a spin-on HSQ film is substituted with a methyl group, a methyl-silsesquioxane (“MSQ”) results.
As stated above, incorporation of porosity in a dielectric film, regardless of its chemical composition, (i.e. organic, inorganic and hybrid) will reduce the film's dielectric value relative to the solid film. This is due to the fact that the dielectric constant of air is nominally 1. As a result dielectric constants are achievable that are lower than 2.5 including values less than 2.0.
One method of forming a particular type of ELK material which forms a porous oxide film is based on a sol-gel process, in which high porosity films are produced by hydrolysis and polycondensation of a silicon alkoxide such as tetraethylorthosilicate. The sol-gel process is a versatile solution process for making ceramic material. In general, the sol-gel process involves the transition of a system from a homogeneous liquid “sol” (mostly colloidal) into a solid “gel” phase. The starting materials used in the preparation of the “sol” are usually inorganic salts or compounds such as silicon alkoxides. The precursor solutions are typically deposited on a substrate by spin on methods. In a typical sol-gel process, the precursor is subjected to a series of hydrolysis and polymerization reactions to form a colloidal suspension, or a “sol.” Further processing of the “sol” enables one to make ceramic materials in different forms. The further processing includes the thermal decomposition of a thermally labile component, which involves the formation of an ordered surfactant-templated mesostructured films by evaporation-induced self-assembly, followed by the thermal decomposition of the template.
In addition to requiring new materials for insulation layers, the trend of decreasing feature size in integrated circuits has created a need for a conductive material having greater conductivity than aluminum which has been the choice in the industry for some time. Many semiconductor manufacturers have turned to copper (Cu) as an interconnect material in place of aluminum, because copper has a lower resistivity and higher current carrying capacity. However, copper has its own difficulties for IC manufacturing processes. For instance, copper diffuses more readily into surrounding materials and hence requires better materials for a barrier layer than traditionally has been used for aluminum. This greater diffuision characteristic exacerbates the low k porosity described above and places even greater emphasis upon the quality of the barrier layers.
An example of an integrated circuit structure which implements copper as an interconnect material is a dual damascene structure. In a dual damascene structure, the dielectric layer is etched to define both the contacts/vias and the interconnect lines. Metal is inlaid into the defined pattern and any excess metal is removed from the top of the structure in a planarization process, such as chemical mechanical polishing (CMP). FIG. 1 shows one example of a dual damascene structure. This structure is appropriate for a first intermetal layer. The integrated circuit 10 includes an underlying substrate 12, which may include a series of layers deposited thereon. The substrate 12 may have transistors therein. A barrier layer 13 may be deposited over the substrate, followed by a dielectric layer 14. The dielectric layer may be undoped silicon dioxide also known as undoped silicon glass (USG), fluorine-doped silicon glass (FSG), or a low k material such as a porous oxide layer or a silicon-carbon or carbon-doped silicon oxide film, or an ELK material. An etch stop layer 16 is deposited over layer 14, pattern etched, and followed by another dielectric layer 18. The structure is then again pattern etched to produce a damascene type pattern. A barrier layer 22 may be needed, which typically has been made from Ta, TaN, Ti, TiN, silicon nitride and plasma enhanced chemical vapor deposited (PECVD) silicon dioxide. However, as explained above, with the smaller feature sizes and increased diffusion propensity of copper, the prior barrier layers are inadequate for optimal performance. Once the conductive material 20 has filled the features, another layer 24, such as a passivation layer, may be deposited. The process described above for a dual damascene structure is exemplary and others may be more appropriate for other particular applications.
Such integration methods when using ELK material and especially porous dielectric materials place additional demands upon the liner or barrier layers. Liner or barrier layers including capping layers such as silicon nitride or silicon dioxide have been deposited adjacent to the low k dielectric layers to prevent the diffusion of byproducts such as moisture and copper. Silicon nitride has been one material of choice for passivation layers. However, silicon nitride has a relatively high dielectric constant (dielectric constant greater than 7.0) and may significantly increase the capacitive coupling between interconnect lines. High dielectric constants result in a capped insulator layer that does not significantly reduce the overall dielectric constant for the combined insulator-capping layer, which defeats the goals of reducing the dielectric constant of the insulating material. Similarly, problems remain in depositing a silicon dioxide capping layer on a porous film. The capping layer is typically deposited in an oxidative PECVD process. Such an oxidative process damages the surface functionality of the underlying porous film and results in degrading the underlying film's chemical properties, which can degrade the low dielectric constant properties of the film. In addition, although silicon-carbide-type material are known to be appropriate for use as barrier or etch stop layers, their use in IC structures using ELK materials and especially porous ELK materials does not appear to be suitable. This is because the lower k silicon carbide-type materials (such as the commercially available Black Diamond™ [k less than 3.0] developed by Applied Materials of Santa Clara, Calif.) are also typically deposited in an oxidative PECVD process, which as described above could damage the underlying porous film, and the higher k silicon-carbide-type films (such as the commercially available BLOk material™ [k less than 4.5] also developed by Applied Materials of Santa Clara, Calif.) may not be suitable because their k value is too high, which could result in an overall capped ELK film stack having too high of a k value.
Therefore, there is a need for a capping layer that will have the lowest dielectric constant possible and one whose deposition process does not damage the underlying ELK film or degrade the underlying film's chemical properties.